Showing posts with label HPC. Show all posts
Showing posts with label HPC. Show all posts

Thursday, February 23, 2012

Engineering and Scientific Subroutine Library (ESSL) and Parallel ESSL

 
ESSL and Parallel ESSL are collections of state-of-the-art mathematical subroutines specifically designed to improve the performance of engineering and scientific applications on the IBM POWER™ processor-based servers and blades. ESSL and Parallel ESSL are commonly used in the aerospace, automotive, electronics, petroleum, utilities and scientific research industries for applications such as:
ESSL and Parallel ESSL support 32-bit and 64-bit Fortran, C and C++ serial, SMP and SPMD applications running under AIX® and Linux®.

ESSL


Sunday, May 8, 2011

Computer configuration for solving large scale MIPs


Here are some recommendations made by Tobias Achterberg on IBM's CPLEX forum on choosing computer hardware for solving large scale MIPs, which is found in AMPL's mailinglist:

Even though the best MIP codes are parallel, they have some critical sequential parts.  Thus single-core computation speed is important, and there is likely to be little useful speedup past 16 or 32 cores.

Large amounts of memory are essential, especially when running in parallel with many cores.  It is worth getting a machine that allows for the largest amount of memory that can be obtained at reasonable cost.

Often the bottleneck is memory bandwidth, so also you want to have the fastest memory you can get.  Note that for current processor chips your computer needs to be equipped with the correct number of RAM DIMMS to get full speed.  This number varies by processor, and must be obtained from information provided by the computer or processor manufacturer.

A reasonable estimate of MIP performance on different chips is given by the SPEC benchmarks at http://www.spec.org/cgi-bin/osgresults?conf=cpu2006.  Do a "Simple Request" for a processor of your choice, look into the "SPECfp2006" tables, and check out the "Base Run Time" of the "450.soplex" test.  The lower the number, the better.

As of March 2011, Tobias's recommended configuration was a dual-processor X5677 (4 cores) or X5680 (6 cores) with six 4GB RAM DIMMS -- at least if your budget permits.  Of course computer technology is constantly evolving and something better will come along soon, if it hasn't already.

Thursday, April 14, 2011

Lehigh University Sixth Annual High Performance Computing Symposium

I am thrilled by the opportunities Lehigh University provides us.  I just finished the first day symposium. My understanding of MPI is strengthened and really appreciate experts from Pittsburgh Supercomputing Center. Actually there are quite useful resources as listed below 

http://www.psc.edu/training/


     The whole program can be reached at
     http://hpcsymposium.lehigh.edu/2011/program.html

Day 1 - Thursday, April 14, 2011

Lehigh University in conjunction with the Pittsburgh Supercomputing Center are pleased to offer a full day of High Performance Computing instruction. Participants will receive a comprehensive introduction to current scientific computing techniques, including a hands-on introduction to distributed computing with MPI. Pittsburgh Supercomputing Center instructors will cover all of the significant computing paradigms such as GPGPU computing and new parallel languages. Students will learn the most popular and effective technique, MPI programming, in detail, followed by hands-on exercises and real problems. Participants are encouraged to bring their own code(s) and seek advice from the instructors. Walk away with the tools necessary to take advantage of the parallel computing facilities available to you at Lehigh. Practical knowledge of C or Fortran is required.

Sunday, March 6, 2011